Electronic circuits are often designed using hardware description languages (HDLs) such as VHDL and Verilog. While very powerful, these languages may obscure understanding of the algorithm to be implemented in hardware.
High-level modeling systems (HLMSs), such as the System Generator HLMS from Xilinx, provide an interface and approach for abstractly specifying a circuit design. Complex circuits may be specified by drawing a network of connected blocks via a graphical user interface (GUI). In the System Generator HLMS, a circuit may be modeled as a system of polymorphic blocks connected by wires that carry signals of application-dependent types. This visual approach is convenient for designing, debugging, and testing a design, as well as for generating a hardware realization of the design.
For added flexibility, the Simulink tool from The MathWorks, Inc., in which the System Generator HLMS operates, enables programmatic creation of block diagrams by way of a command language for adding blocks and connecting ports between blocks. However, this command interface may be tedious and error prone because the user is required to explicitly specify connectivity and sometimes specify placement of the blocks. Furthermore, parameterizing the blocks created with the command language may be difficult.
The present invention may address one or more of the above issues.